High-gain multistage amplifiers are often used to amplify signals having relatively small amplitudes, i.e., having relatively low power. For example, such amplifiers are typically used to amplify signals received via optical fibers.
But without adequate offset compensation, such multistage amplifiers often have relatively large output DC-offset voltages. Specifically, each stage of a high-gain amplifier typically generates an unwanted low-frequency, i.e., direct-current (DC), offset voltage at its output node(s). This output DC-offset voltage is defined as a stage's output voltage when the stage's input voltage is 0 Volts (V). Typically, the ideal output DC-offset voltage for a single-ended stage is half way between the stage's supply voltages, and the ideal output DC-offset voltage for a differential stage is 0V. Such an ideal DC-offset voltage allows the stage to generate an amplified high-frequency, i.e., alternating-current (AC), output signal having the largest unclipped peak-to-peak voltage possible for a given set of supply voltages. But if the output DC-offset voltage has a non-ideal level, then the AC output signal's maximum peak-to-peak voltage is reduced by twice the difference between the actual and ideal levels of the DC-offset voltage. For example, suppose a single-ended amplifier stage has +5V and −5V power supplies and an output-voltage range of +4V and −4V. If the stage's DC-offset voltage is an ideal 0V (halfway between +5V and −5V), then the stage can generate an amplified output signal having a peak-to-peak voltage as large as 8V. But if the DC-offset voltage is +1V, then the output signal's maximum peak-to-peak voltage is reduced to 6V. In a multistage amplifier, each latter stage amplifies the DC-offset voltage of each former stage. Therefore, even in amplifiers with relatively few stages having relatively low DC-offset voltages, the cumulative DC-offset voltage at the output of the last stage can be quite large.
Consequently, to maintain the output DC-offset voltage at a desirable level, a multistage amplifier typically includes an offset-compensation circuit. A common type of offset-compensation circuit uses negative feedback to maintain the output DC-offset voltage at a desirable level.
But unfortunately, as discussed below in conjunction with FIGS. 1 and 2, available offset-compensation circuits typically cannot provide desired levels of compensation over a large range of input-signal power or over a large range of amplifier gains.
FIG. 1 is a block diagram of a conventional differential high-gain multistage amplifier 10 that generates an output signal Vout by amplifying an input signal Vin and that includes a feed-forward amplification path 12 and a single offset-compensation path 14.
The amplification path 12 includes serially coupled differential amplifier stages 161, 162, . . . , and 16n, which have respective input DC-offset voltages Voffin1, Voffin2, . . . , and Voffinn and which generate output DC-offset voltages Voffout1, Voffout2, . . . , and Voffoutn. Each stage 16 has a respective pair of differential input nodes 18a and 18b and a respective pair of differential output nodes 20a and 20b. In addition, the stage 161 has a pair of differential offset-adjust nodes 22a1 and 22b1. A common technique for modeling the input DC offsets Voffin1, Voffin2, . . . , and Voffinn is to include DC-offset sources 241, 242, . . . , 24n, which are serially coupled to the input nodes 18a1, 18a2, . . . , and 18an, respectively. Therefore, Voffout1=Voffin1×Gdc161, Voffout2=(Voffout1+Voffin2)×Gdc162, . . . , and Voffoutn=(Voffoutn−1 +Voffinn)×Gdc16n, where Gdc161, Gdc162, . . . , and Gdc16n represent the DC gains of the amplifier stages 161, 162, . . . , 16n, respectively. Consequently, a relatively small input DC-offset voltage generated by a stage at the front end of the amplifier 10 can cause a relatively large DC-offset voltage Voffoutn across the amplifier's output nodes 20an and 20bn. For example, if the number of stages n=3, Voffin1=1 nanoVolt (nV), and Gdc161, Gdc162, and Gdc163=1000, then Voffout3=1 nV×1000×1000×1000 1 V, which is often too large for proper operation of the amplifier 10.
Furthermore, the amplifier stages 161, 162, . . . , 16n amplify Vin to generate respective output voltages of interest Vsout1, Vsout2, and Vsoutn. Therefore, assuming that Vin is an AC signal, Vsout1=Vin×Gac161, Vsout2=Vsout1×Gac162, . . . , and Vsoutn=Vsoutn-1×Gac16n, where Gac161, Gac162, and Gac16n are the AC gains of the stages 161, 162, . . . , and 16n, respectively.
Consequently, if the output DC-offset voltage Voffout of an amplifier stage 16 is too high, then the stage may clip the output voltage Vsout of interest. Using the well-known superposition theorem, the combined output voltages generated by the stages 161, 162, . . . , and 16n, respectively, are Vsout1+Voffout1, Vsout2+Voffout2, . . . , and Vsoutn+Voffoutn=Vout. Therefore, the signal components of interest Vsout1–Vsoutn“ride” on the offset components Voffout1–Voffoutn, respectively. For example, suppose that Voffoutn is an ideal 0 V and that the differential peak-to-peak range of the last stage 16n is 4 V. Therefore, if Vsoutn is a sinusoid with a peak-to-peak amplitude of 3 V, then the stage 16n generates Vsoutn with no clipping. But if Voffoutn=1 V, then the stage 16n will clip Vsoutn.
To reduce the output DC-offset voltage of the amplifier stages 16 to acceptable levels so as to prevent clipping, the amplifier 10 includes the feedback compensation path 14, which includes a compensator 26 for maintaining the output DC-offset voltage of a selected stage 16—here the stage 162—at a predetermined level. Specifically, the compensator 26 receives the output DC-offset voltage of the selected stage 162 on differential input nodes 28a and 28b, generates on output nodes 29a and 29b a differential correction signal OFFSET ADJUST having a value that is related to the level of the received DC offset, and provides OFFSET ADJUST to a prior stage 16—here the first stage 161. OFFSET ADJUST alters the output DC-offset voltage of the prior stage 161 so as to maintain the output DC offset of the selected stage 162 at the predetermined level. More specifically, in the example shown in FIG. 1, the compensator 26 is a high-gain amplifier that uses negative feedback to maintain the output DC-offset voltage of the stage 162 at or near 0 V. The compensator 26 receives the output voltage Vsout2+Voffout2 from the output nodes 20a2 and 20b2 of the stage 162. Because the purpose of the compensator 26 is to control the level of Voffout2, it filters out the higher-frequency component Vsout2 with a low-pass filter (not shown in FIG. 1) to isolate Voffout2. Then, it generates OFFSET ADJUST from the isolated Voffout2 and provides OFFSET ADJUST to the adjust terminals 22a and 22b of the first stage 161. In response to OFFSET ADJUST, the stage 161 adjusts its output DC-offset voltage Voffout1 to a level that causes Voffout2 to equal or approximately equal 0 V.
Although the feedback path 14 can maintain the output DC-offset voltage Voffout2 of the selected amplifier 162 at a desired level, the last amplifier stage 16n may generate an undesirably large output DC-offset voltage Voffoutn, particularly when Vsoutn is relatively low power. This is because Voffoutn may overpower Vsoutn, thus making Vsoutn difficult to recover. Such low-power Vsoutn is typically caused by Vin having a relatively low power.
FIG. 2 is a block diagram of an amplifier 30 that attempts to solve this problem by replacing the single feedback path 14 with a single feedback path 32 that is connected to the output nodes 20an and 20bn of the last stage 16n. Except for the different feedback path 32, the amplifier 30 is the same as the amplifier 10 of FIG. 1 and thus like numbers are used to reference like components in FIGS. 1 and 2.
In operation, the compensator 26 receives the differential output voltage Vsoutn+Voffoutn from the output nodes 20an and 20bn of the last stage 16n, filters out the higher-frequency component Vsoutn to isolate Voffoutn, generates OFFSET ADJUST from the isolated Voffoutn, and provides OFFSET ADJUST to the first stage 161. In response to OFFSET ADJUST, the stage 161 adjusts its output DC-offset voltage Voffout1 to a level that causes Voffoutn to equal or approximately equal 0 V.
But a problem with the amplifier 30 is that the output-signal component Vsoutn may be so large that the compensator 26 cannot accurately adjust the DC offset Voffoutn to a desired level. A large Vsoutn is typically caused by a high-power input signal Vin. As discussed above in conjunction with FIG. 1, if Voffoutn and Vsoutn are too large, then the stage 16n may clip Vsoutn. But if the stage 16n clips Vsoutn, then low-pass filtering Vout yields the DC component of the clipped Vsoutn, not the true DC offset Voffoutn. Therefore, the compensator 26 isolates this DC component instead of Voffoutn, and thus erroneously generates OFFSET ADJUST from this isolated component. Consequently, because OFFSET ADJUST is inaccurate, the stage 161 typically does not adjust Voffout1 to a value that causes Voffoutn to equal or approximately equal a desired level such as 0 V.
Therefore, referring to FIGS. 1 and 2, although the offset-compensation path 14 renders the amplifier 10 well suited for a relatively large voltage signal Vsoutn and the offset-compensation path 32 renders the amplifier 30 well suited for a relatively small Vsoutn, neither the amplifier 10 nor the amplifier 30 works well over an entire of amplitudes for Vsoutn. And because the amplitude of Vsoutn is proportional to the power of Vin neither the amplifier 10 nor the amplifier 30 works well over an entire range of powers for Vin.